1. Field of the Invention
The present invention relates to field effect transistors and integrated circuits and, particularly, to a field effect transistor (FET) having a gate electrode with a reduced gate resistance and a method for fabricating the same.
2. Description of the Related Art
The manufacturing process of integrated circuits (ICs) involves the fabrication of numerous semiconductor devices, such as insulated gate field effect transistors, on a single substrate. In order to provide increased integration density and an improved device performance of the field effect transistors, for instance, with respect to signal processing time and power consumption, feature sizes of the field effect transistors are steadily decreasing. In general, decreasing feature sizes, such as the gate length of the field effect transistor, provide a variety of advantages, for example, high package density and small rise and fall times during switching of the transistors due to the reduced gate length and, hence, the reduced channel length. Reducing the gate length of the FET beyond a certain size, however, may result in disadvantages that act to offset advantages obtained by the reduced channel length, e.g., the resistance of the gate electrode having the reduced gate length increases with decreasing gate length. As a result, a delay of the voltage applied to the gate electrode for controlling the channel can be observed. Especially in modern ultrahigh density circuits, the gate length is trimmed down to 100 nm or less, so that the available gate cross-section for transmitting the voltage applied to the gate electrode is not sufficient to insure the high-speed signal transmission required for obtaining the fast switching times of modern integrated circuits, such as microprocessors driven by clock frequencies of 1 GHz and more.
To clearly demonstrate the problems involved with steadily decreasing feature sizes of modern ultra-high density integrated circuits, a typical prior art process flow will be described with reference to FIGS. 1a-1d, in which the problems involved with the formation of the gate electrode are detailed. As the skilled person will easily appreciate, the figures depicting the typical prior art process flow and the typical prior art device are merely of a schematic nature, and transitions and boundaries illustrated as sharp lines may not be imparted as sharp transitions in a real device. Furthermore, the description of the typical prior art process and device refers to standard manufacturing procedures without specifying typical process parameter values used for these procedures, since individual processing steps may be accordingly adapted to meet specific design requirements. Moreover, only the relevant steps and features of the transistor device are shown in the figures.
In FIG. 1a, a schematic cross-sectional view of a field effect transistor manufactured in accordance with a typical CMOS processing is illustrated. In FIG. 1a, a field effect transistor 100 is schematically shown in a manufacturing stage prior to patterning a gate electrode. In a silicon substrate 101, shallow trench-isolations 102 define an active region 106. A gate insulation layer 103 separates a polysilicon layer 104 from the active region 106. On the polysilicon layer 104, a photoresist layer 105 is patterned.
The formation of the structure shown in FIG. 1a may be accomplished using the following process steps. After defining the active region 106 by forming the shallow trench isolations 102, the gate insulation layer 103 is thermally grown on the substrate. Thereafter, a polycrystalline silicon (polysilicon) layer 104 is deposited over the gate insulation layer 103. Then, a photoresist layer is deposited on the polysilicon layer 104, and it is patterned by photolithography using deep ultraviolet exposure light to result in the patterned photoresist layer 105.
FIG. 1b schematically shows a cross-sectional view of the field effect transistor 100 of FIG. 1a in an advanced manufacturing stage. In FIG. 1b, a gate electrode 107 is formed over the active region 106, and it is separated therefrom by the gate insulation layer 103. The gate electrode 107 has been formed from the polysilicon layer 104 by anisotropic etching using the photoresist layer 105 as a mask. A lateral extension of the gate electrode 107 in a transistor length dimension, indicated by the arrows 108 and 109 and also referred to as the gate length, is determined by the lithography step and by a subsequent etch trim process performed to further reduce the gate length. A gate height, indicated by arrow 110, is determined by the thickness of the polysilicon layer 104. According to this typical prior art processing, the gate length on the top 120 of the gate electrode 107, as indicated by arrow 109, is essentially equal to the gate length at the foot or bottom 141 of the gate electrode 107, represented by arrow 108.
As can be seen from FIG. 1b, the cross-section of the gate electrode 107 is of substantially rectangular shape and the effective cross-section available for charge carrier transportation decreases, as the gate length is scaled down. Moreover, the gate voltage for controlling the channel to be formed in the active region 106 is applied by contact portions that are outside of the active region in the transistor width dimension, which is the dimension extending along a line normal to the drawing plane of FIG. 1b. Accordingly, the effective sheet resistance of the gate electrode depends on the gate length on the top portion 120 of the gate electrode 107, and, more particularly, the gate sheet resistance increases as the gate length decreases.
FIG. 1c schematically shows a cross-section of the final field effect transistor 100. In the active region 106, drain and source regions 111 are formed and separated in the transistor length dimension by a channel 114. Sidewall spacers 112 are formed on the sidewalls of the gate electrode 107 and extend along the transistor width dimension. At the top surfaces of the drain region, the source region and the gate electrode, portions 113 of materials having a reduced electrical resistance, for example, consisting of cobalt silicide, are formed.
The portion 113 of reduced electrical resistance above the gate electrode 107 is also of substantially rectangular shape and, therefore, exhibits a gate area available for charge carrier transportation, i.e., cross-section that is small, particularly when the gate length is trimmed down to dimensions of 100 nm and beyond. Since the thickness of the polysilicon layer 104 and, hence, the height of the gate electrode 107, is limited to about 1500-2000 xc3x85 with respect to stability of the gate electrode, polysilicon delamination and the like, the transistor 100 suffers from higher gate resistance when the gate length is reduced, thereby significantly deteriorating the performance of the transistor.
In view of the above problems, a need exists for a field effect transistor device having a reduced gate resistance, and for a method for fabricating the gate electrode with reduced gate resistance.
According to one aspect of the present invention, a transistor comprises a substrate, an active region defined in the substrate, a gate insulation layer formed above the active region, and a gate electrode formed above the gate insulation layer. The gate electrode comprises a middle portion located over the active region, wherein the middle portion has a gate length and a gate height. A cross-sectional area in a plane defined by the gate length and the gate height of the middle portion exceeds a value obtained by multiplying the gate length by the gate height.
As is common practice, the gate length is herein defined as the lateral extension at the bottom of the middle portion of the gate electrode. The middle portion indicates that part of the gate electrode is located over the channel region for controlling the conductivity of the channel. The gate height is defined as the extension of the gate electrode perpendicular to the surface of the active region on which the gate insulation layer is formed. Thus, according to the present invention, the gate electrode comprises a middle portion that may be scaled down to meet the design requirements such that a reduced channel length can be realized, wherein the cross-sectional area is increased compared to a typical prior art device having a substantially rectangular cross-sectional area. As a consequence, the effective gate resistance is decreased and the device performance with respect to, for example, signal delay, is significantly improved.
In accordance with a further embodiment of the present invention, a lower part of the middle portion may be formed such that its lateral extension, i.e., its length dimension, along the gate height dimension is substantially uniform, that is the cross-section is substantially rectangular, and the lateral extension substantially coincides with the gate length. Thus, a xe2x80x9cstep-likexe2x80x9d transition from the lower part to an upper part of the middle portion of the gate electrode is provided. The lateral extension of the upper part of the gate electrode at this transition is significantly larger than the gate length. This xe2x80x9cT-shapedxe2x80x9d cross-section of the middle portion of the gate electrode provides an increased cross-section area and, thus, the effective gate resistance is significantly reduced. Moreover, due to the present invention, the top surface of the gate electrode is also increased and results in a decreased gate sheet resistance of the gate electrode, which also contributes to an improved signal transmission of the gate electrode. Furthermore, due to an increased surface area, a portion of reduced electrical resistance, for example, comprising a metal, is also increased and, hence, the effective electrical resistance of the gate electrode is further decreased, regardless of the gate length.
According to another aspect of the present invention, a method of manufacturing a field effect transistor having an improved signal performance is provided. The method comprises providing a substrate and forming an active region thereon, forming a gate insulation layer over the active region, and depositing a first gate electrode material having a first thickness and patterning a first portion of a gate electrode, wherein the first portion has a height substantially equal to the first thickness. The method further comprises depositing an insulating layer having a thickness determined by the first thickness, planarizing the insulating layer to expose a surface of the first portion, selectively removing material of the planarized insulating layer so as to reduce the thickness of the insulating layer until a predefined adjustment thickness is obtained to partially expose the sidewalls of the first portion, depositing a second gate electrode material layer over the insulating layer and the first portion, and anisotropically etching the second gate electrode material layer to form a gate electrode including the first portion and an extension portion laterally extending beyond the first portion, wherein a cross-sectional shape of the extension portion is determined by the adjustment thickness.
According to the method of the present invention, the gate electrode is formed in two steps, wherein the first step determines the final gate length of the transistor and the second step provides for the extension portion to significantly increase the cross-section of the gate electrode. Moreover, the method allows defining a cross-sectional shape of the gate electrode by adjusting the thickness of the insulating layer so that the resulting cross-sectional area of the gate electrode can be reliably and reproducibly obtained, since the deposition and etching processes involved in forming and patterning the insulating layer are well-controllable.
In accordance with further embodiments of the present invention, the process of selectively removing material of the insulating layer comprises using a slow chemical etch solution that is highly selective with respect to the first gate electrode material layer. Alternatively, selectively removing the insulating layer may comprise forming one or more etch stop layers on the first portion prior to the deposition of the insulating layer. Hence, the method can easily be implemented into a standard process flow so as to guarantee efficiency and cost-effectiveness of the manufacturing process. Moreover, according to the present invention, the gate electrode having an extension portion with increased lateral extension does not require any additional cost-intensive photolithography and, hence, does not require any additional aligning steps. This characteristic is also referred to as a xe2x80x9cself-alignedxe2x80x9d process.
Further advantages and objects of the present invention will become more apparent from the following detailed description and the appended claims.